Informations générales
Number of hours
- Lectures 16.0
- Projects -
- Tutorials 12.0
- Internship -
- Laboratory works -
- Written tests 2.0
ECTSECTS
0.5
Goal(s)
The digital design part targets methods and tools used in system design and also the bases of the Computer-Aided-Design tools (logic synthesis, High level synthesis, Data-path-FSM architecture).
The FPGA prototyping covers the design and implementation of a complete embedded system based on a RISC processor (RISC-V). This processor is able to execute the RISCV RV32I instruction set.
At the end of this course, students will be able to :
- Design digital circuits given a functionality specification and a set of basic components
- Master a 32-bit RISC processor architecture (RISC-V)
- Understand the principles of VGA display
- Simulate and synthesize the architecture of a complete embedded system using Xilinx Vivado tools.
Content(s)
1. Digital Design :
- Bool functions and basics
- Optimization et factorization of boolean functions (Quine - Mc Kluskey method)
- Logic synthesis
- Data-path and control parts of a chip
- Control part synthesis
- High level synthesis
2. Introduction to FPGA programmable circuits :
- Examples of FPGA architectures
- FPGA design flow
3. Integrator project :
- Implementation of 32-bit processor instructions (RISC-V)
- Validation of instructions by simulation and testing on prototyping board
- Design, simulation and synthesis of test programs: led counter, minimalist led chaser, pattern rotation chaser
- Control of a 7-segment display
- Software applications on RISC-V processor: invaders, pong, brick, snake
- Basic knowledge of digital electronic systems
- Notions of combinatorial and sequential circuits
- Module "Algorithms and programming" (IESE3 - 5th & 6th semester)
- Module "Microcontroller" (IESE3 - 5th & 6th semester)
- Module "Processor architecture" (IESE5 - 9th semester)
- Module "VHDL" (IESE4 - 9th semester)
Calendar
The course exists in the following branches:
- Curriculum - IESE - Semester 9
Additional Information
Course ID : KAIE9M16
Course language(s): 
You can find this course among all other courses.
Bibliography
Conception avancée:
- The Synthesis Approach to Digital System Design, P. Michel et al., Kluwer Academic Publishers, 1992
- Behavioral Synthesis and Component Reuse with VHDL, A. A. Jerraya et al., Kluwer Academic Publishers, 1997
- Conception Logique et Physique des Systèmes Monopuces, A. Jerraya et al., Hermes, 2002 (in French)
- Conception de Haut Niveau des Systèmes Monopuces, A. Jerraya et al., Hermes, 2002 (in French)
- Algorithms for VLSI Design Automation, S. Gerez, Wiley, 1999
- Architectures Logicielles et Matérielles, P. Amblard et al., Dunod, 2000 (in French)
Prototypage:
- "1076-2008 - IEEE Standard VHDL Language Reference Manual" par IEEE
- "VHDL : Programming by Example" 4th Edition, par Douglas L. Perry
- "Computer Organization and Design - The Hardware/Software Interface" (RISC-V Edition), par David A. Patterson et John L. Hennessy
- The RISC-V Reader: An Open Architecture Atlas, David Patterson and Andrew Waterman, 2017