Number of hours
- Lectures 8.0
- Projects -
- Tutorials -
- Internship -
- Laboratory works 20.0
- Written tests 4.0
ECTS
ECTS 0.3
Goal(s)
This course introduces the hardware description language VHDL. It offers different tools to learn the multiple design possibilities provided by VHDL.
Following this course, students will be able to:
- Model electronic systems with VHDL
- Design synchronous circuits as finite-state machines
- Understand logical synthesis and essential constructs used in the design flow
- Verify theory with practical examples (simulation)
Content(s)
- Modeling and simulation of electronic systems
- Principles of VHDL language
- Model structure and data types
- Data flow and structural VHDL description levels
- Concurrent and sequential instructions
- Sequential and combinatorial logic circuits
- Advanced aspects: packaging, subroutines, generics and generate statements, conversion functions
- Basic knowledge of digital electronic systems
- Programming basics
- Basic knowledge of Boolean algebra
- Notions of combinatorial and sequential circuits
Test
30% CC + 70% final exam
Final exam conditions :
- 1 practical exam – 4h
- Course material and practice codes authorized
- Calculator, personal computer, mobile phone and smartwatch forbidden
- Third time: same duration with score * 1.33
Calendar
The course exists in the following branches:
- Curriculum - E2I - Semester 9
Additional Information
Course ID : KAEL9M06
Course language(s):
You can find this course among all other courses.
Bibliography
- "1076-2008 - IEEE Standard VHDL Language Reference Manual" par IEEE
- "VHDL - langage, modélisation, synthèse" 2ème édition, par Roland Airiau, Jean-Michel Bergé, Vincent Olive et Jacques Rouillard
- "The Designer's Guide to VHDL" 3rd Edition, par Peter J. Ashenden et Jim Lewis
- "VHDL : Programming by Example" 4th Edition, par Douglas L. Perry