Digital design - KAIE9M17

  • Number of hours

    • Lectures 24.0
    • Projects -
    • Tutorials 10.0
    • Internship -
    • Laboratory works 8.0
    • Written tests 2.0

    ECTS

    ECTS 0.5

Goal(s)

First part (CL1): digital system design based on MOS transistors, basic cells

Second part (CL2): Method and tools used in system design, base of the Computer-Aided-Design tools (logic synthesis, High level synthesis, Data-path-FSM architecture)

Content(s)

CL1 :
The CMOS transistor
CMOS inverter
Basic CMOS gates
Optimizations of CMOS gates

CL2 :
Bool functions and basics
Optimization et factorization of boolean functions (Quine - Mc Kluskey method)
FPGA architecture
Logic synthesis
Data-path and control parts of a chip
Control part synthesis
High level synthesis

Prerequisites

Basics in digital and analog electronics, basics in diods and transistors

Test

35% CC (CL1) + 65% final exam (written - 2h no document)

Calendar

The course exists in the following branches:

  • Curriculum - IESE - Semester 9

Additional Information

Course ID : KAIE9M17
Course language(s): FR

You can find this course among all other courses.

Bibliography

The Synthesis Approach to Digital System Design
P. Michel, U. Lauther, P. Duzy (éditeurs), Kluwer Academic Publishers, 1992
ISBN : 0-7923-9199-3

Behavioral Synthesis and Component Reuse with VHDL
A. A. Jerraya, H. Ding, P. Kission, M. Rahmouni, Kluwer Academic Publishers, 1997
ISBN : 0-7923-9827-0

Conception Logique et Physique des Systèmes Monopuces
Sous la direction de A. Jerraya, Hermes, 2002 (in French)
ISBN : 2-7462-0434-7

Conception de Haut Niveau des Systèmes Monopuces
Sous la direction de A. Jerraya, Hermes, 2002 (in French)
ISBN : 2-7462-0433-9

Algorithms for VLSI Design Automation
S. Gerez, Wiley, 1999
ISBN : 0-471-98489-2

Architectures Logicielles et Matérielles
P. Amblard, J.C. Fernandez, F. Lagnier, F. Maraninchi, P. Sicard, P. Waille, Dunod, 2000 (in French)
ISBN : 2-10-004893-7